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NXP Semiconductors /MIMXRT1021 /ADC1 /HC0

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Interpret as HC0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADCH0 (AIEN_0)AIEN

AIEN=AIEN_0

Description

Control register for hardware triggers

Fields

ADCH

Input Channel Select

16 (ADCH_16): External channel selection from ADC_ETC

25 (ADCH_25): VREFSH = internal channel, for ADC self-test, hard connected to VRH internally

31 (ADCH_31): Conversion Disabled. Hardware Triggers will not initiate any conversion.
AIEN

Conversion Complete Interrupt Enable/Disable Control

0 (AIEN_0): Conversion complete interrupt disabled

1 (AIEN_1): Conversion complete interrupt enabled

Links

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Register License

Copyright 2016-2020 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data